This invention relates to a ferroelectric random-access memory.
It is known to use a ferroelectric capacitor as the principal part of a nonvolatile memory cell, namely, a memory cell that retains the stored data even though the power is turned off. A ferroelectric material, represented by lead zirconate titanate (PZT), is very high in relative permittivity (dielectric constant), makes spontaneous polarization and possesses hysteresis of polarization with changes in the direction of polarization. A ferroelectric capacitor has a ferroelectric film sandwiched between a pair of electrode plates.
Nonvolatile ferroelectric random-access memories are described, for example, in U.S. Pat. No. 4,873,664, JP-A 1-158691 and ISSCC (International Solid-State Circuits Conference) Digest of Technical Papers, Feb. 1994, pp. 268-269. Known ferroelectric memories use either a 1T/1C memory cell consisting of a ferroelectric capacitor and a field effect transistor or a 2T/2C memory cell having two ferroelectric capacitors and two field effect transistors. In general, the 1T/1C cell is preferable for enhancement of the level of integration.
FIG. 1 shows a 1T/1C memory cell 10 having a ferroelectric capacitor 12 and a field effect transistor 14 for switching. One electrode plate of capacitor 12 is coupled to a bit line BL by the source-drain path of transistor 14, and the other plate of the capacitor is coupled to a plate line PL. The gate electrode of transistor 14 is coupled to a word line WL.
Capacitor 12 can store either logic "1" or logic "0" according to the state of polarization of the ferroelectric material (not shown) between the two plates. FIG. 2 shows a hysteresis loop of polarization of the ferroelectric in capacitor 12. The abscissa represents external voltage V applied across the two plates of the capacitor, and the ordinate represents polarization charge Q on the ferroelectric between the two plates. The ferroelectric assumes a stable state at point A on the hysteresis loop and another stable state at point E. So, point A can represent logic "0", and point E can represent logic "1". When a voltage -V.sub.e is applied across the two plates of capacitor 12 while transistor 14 is conducting, the charge stored in the capacitor is fed out onto bit line BL. The amount of the charge is Q.sub.0 if the ferroelectric is in the state at point A, and Q.sub.1 if the ferroelectric is in the state at point E. A resulting change in voltage on the bit line is detected by a sense amplifier, which is a differential amplifier, by comparison with a reference voltage which is impressed on another bit line (not shown). The reference voltage is intermediate between a voltage developed on bit line BL by the charge Q.sub.1 and another voltage developed on bit line BL by the charge Q.sub.0.
As a result of the transfer of charge Q.sub.1 or Q.sub.0 from capacitor 12 to bit line BL, the polarization state of the capacitor changes to point H in FIG. 2, meaning that the originally stored data is lost. The lost data is regenerated by applying a positive voltage V.sub.e or 0 volt across capacitor 12.
FIG. 7 shows a 2T/2C memory cell 10A having two ferroelectric capacitors 12, 12' and two transistors 14, 14'. Capacitor 12 is coupled to a bit line BL1 via the source-drain path of transistor 14, and capacitor 12' to another bit line BL2 via the source-drain path of transistor 14'. A word line WL is common to the two transistors, and a plate line PL is common to the two capacitors. In this memory cell the two capacitors are forced to polarize in opposite directions. For example, the memory cell stores logic "1" when the polarization state of capacitor 12 is at point E in FIG. 2 while the state of capacitor 12' is at point A, and stores logic "0" when the states of the two capacitors are reverse. When a voltage -V.sub.e is applied across the two plates of the both capacitors while, for example, the memory cell stores logic "1", charge Q.sub.1 is fed from capacitor 12 onto bit line BL1 and charge Q.sub.0 from capacitor 12' onto bit line BL2. A resulting voltage difference between bit lines BL1 and BL2 is detected and amplified by a sense amplifier. When charges Q.sub.1 and Q.sub.0 move onto bit lines BL1 and BL2, the polarization state of both capacitors 12 and 12' changes to point H in FIG. 2, meaning loss of the originally stored data. To regenerate the lost data, a positive voltage V.sub.e and 0 volt are applied to capacitors 12 and 12', respectively.
In known ferroelectric memories, positive and negative voltages are alternately applied across the two plates of the capacitor(s) of the accessed memory cells to read out the stored data and regenerating the data. For this purpose, it is usual to shift the plate line potential from low level to high level or reversely by proper clocking. However, for the following reason, clocking of the plate line potential is unfavorable for enhancement of operation speed. Ferroelectric capacitors have large capacitance values since ferroelectric materials have large dielectric constants. In practice, plate line is a metal film which is usually formed of a noble metal such as Au, Pt or Ru in view of compatibility with ferroelectric materials. The thickness of plate line film is limited because thick films of these noble metals are rather inferior in processability, whereas enlargement of the plate line width is against the desire for higher integration of memory cells. So, plate line has a relatively large resistance value and, coupled with ferroelectric capacitors having large capacitance values, has a relatively large time constant. Therefore, time lags needed for clocking of the plate line potential become significant. Besides, relatively large power is consumed for shifting the plate line potential.
To obviate the above disadvantages, there are proposals of fixing the plate line potential at a suitable level. For example, JP-A 2-110895 proposes the following technique.
The plate line potential is always fixed at an intermediate voltage between low level (ground potential) and high level (level of supply voltage). During standby periods, bit lines (or bit line pairs) are kept at the intermediate voltage. In reading operation, the voltage on bit line (or bit line pair) for the accessed memory cell is shifted to low level or high level to impress a voltage -V.sub.e or +V.sub.e across the two plates of the capacitor to thereby transfer a charge corresponding to the state of polarization from the capacitor to bit line. After that the data is regenerated by applying a voltage in the reverse direction to the capacitor, and then the voltage on bit line is shifted to the intermediate voltage.
In this case it is necessary to continuously produce the intermediate voltage by treating supply voltage and to supply the produced voltage to plate line. Therefore, a considerable increase in power consumption is inevitable.
In ferroelectric memories, read and/or write operations cause reversals of the direction of polarization of the ferroelectric material in the capacitors. A reversal of the direction of polarization means that the state of polarization moves from point F (in FIG. 2) to point G or from point B to point C. In most of known ferroelectric capacitors, the amount of charge that can be taken out of the capacitor (Q.sub.1 in FIG. 2) decreases as reversals of the direction of polarization are repeated innumerable times. This phenomenon is called fatigue of ferroelectric film. If the fatigue becomes significant, the stored data is destructed.
To retard fatigue of the ferroelectric in ferroelectric memories, it is possible to operate the memory without causing reversal of the direction of polarization on condition that the power is kept on. In this method, the state of polarization of the capacitor of the 1T/1C memory cell of FIG. 1 is, for example, at point D (in FIG. 2) to store logic "1" and at point E to store logic "0". The plate line potential is fixed to ground potential (or supply voltage), and the bit line BL is precharged to a voltage intermediate between supply voltage and ground potential together with a complementary bit line which is not coupled to the selected memory cell. Transistor 14 is turned on after interrupting precharging of bit lines. Then a current flows out of the capacitor onto bit line BL if the stored data is logic "1", and a current flows from bit line BL into the capacitor if the stored data is logic "0". A resulting change in the voltage on bit line BL is detected by comparison with the intermediate voltage on the complementary bit line. By this read operation the state of polarization of the capacitor moves from point D or E to point C, and the original state of point D or E is resumed when the voltages on bit line BL and the complementary bit line are shifted to supply voltage and ground potential, respectively.
In this method the voltages across the capacitor are always in a specific direction. Therefore, there occurs no reversal of the direction of polarization of the ferroelectric. That is, the ferroelectric capacitor acts as an ordinary dielectric capacitor, and the memory cell functions in the same manner as memory cells of a conventional DRAM. This method is operating ferroelectric memory cells in a volatile mode since the stored data is destructed if the power is turned off. That is, if the voltage across the capacitor becomes 0, the state of polarization moves to point E irrespective of the original state, and hence it becomes impossible to discriminate between logic "1" and logic "0".